A semiconductor intellectual property (IP) core, IP block, or core refers to a reusable unit of logic, cell, or chip layout design that is owned by an entity. The core may be licensed to another party or can be owned and used by a single party. In digital logic applications, cores are typically offered as generic gate netlists. The netlist is a Boolean representation of the core's logical function. Some vendors offer synthesizable versions of their cores. Synthesizable cores are delivered in a hardware description language, such as Verilog or VHDL, permitting customer modification at the functional level.
Cores are implemented with physical circuits. Testing of physical circuits is typically performed in accordance with a Test Access Protocol (TAP). JTAG, an acronym for Joint Test Action Group, is the name used for the IEEE 1149.1 standard entitled Standard Test Access Port and Boundary-Scan Architecture. While designed for printed circuit boards, JTAG is commonly used for testing sub-blocks of integrated circuits and is also used for debugging embedded systems. When used as a debugging tool, an in-circuit emulator, which in turn uses JTAG as the transport mechanism, enables a programmer to access an on-chip debug module which is integrated into the core. The debug module enables the programmer to debug the software of an embedded system.
JTAG supports the serial scan of test data between multiple cores within a single system. In order to communicate with a single core, the TAP controller serially scans through all of the TAP chains. Non-addressed cores can be placed in a bypass mode to minimize the total length of the TAP chain. However, placing non-addressed cores into bypass mode incurs an overhead cost.
In view of the foregoing, it would be desirable to provide an improved technique for accessing and testing individual cores in a multiple core system.